The present invention relates to a semiconductor device in which a part of the semiconductor substrate is isolated from the rest of it through an insulation layer, and at least one semiconductor device is formed in this isolated region.
Generally, in semiconductor integrated circuits, a number of integrated circuit elements, for example, transistors, diodes, resistors, capacitors, etc. are formed in one chip and these integrated circuit elements are isolated from one another. In the ordinary MOS type integrated circuit, the isolation is effected in only the planar direction. In this case, a thick oxide film, which is called a field oxide film, is formed outside the element region. Impurities of the same conductivity type as that of the substrate are generally introduced by ion implantation into the region below the field oxide film in order to prevent inversion of the field layer. In the integrated circuit of this construction, the circuit elements are electrically connected to each other via the substrate.
What should be noted is that erroneous operations of the integrated circuit such as crosstalk between the circuit elements, latch-up in the case of a CMOS structure and soft error caused by .alpha.-ray tend to accompany the minimization of the circuit elements. When it comes to an integrated circuit of a high reliability which permits suppressing, particularly, the erroneous operations mentioned above, there is an isolation method for isolating the semiconductor region, in which, one or more integrated circuit elements are formed, from the substrate by an insulation layer. By forming a CMOS device using this isolation method, it is possible to construct a semiconductor device in which the latch-up phenomenon is suppressed and soft errors due to the .alpha. rays are reduced. In addition, the use of the insulation layer reduces stray capacitance between each integrated circuit element and the ground so that this integrated circuit element can be operated at a high operation speed.
There are three examples of the foregoing isolation method for isolating the element formation area from the substrate:
(1) A method in which a monocrystalline silicon layer is directly formed on an insulation substrate such as a sapphire substrate or the like by a vapor phase growth;
(2) A method in which a silicon oxide layer is formed on a silicon substrate and a polysilicon layer or amorphous silicon layer is formed on this oxide layer and thereafter a monocrystalline silicon layer is formed by melting those layers with an electron beam or laser beam or by way of solid phase growth;
(3) A method in which an insulation layer is formed so as to surround a predetermined area of a monocrystalline silicon substrate and a monocrystalline silicon layer is left only in this predetermined area and is used to form a semiconductor active region which is isolated from the semiconductor substrate.
Semiconductor elements are actually manufactured for sale using the isolation method (1). However, sapphire used as a substrate is so expensive, and thus the cost of the semiconductor device is extremely high.
In the case of forming a semiconductor device by the isolation method (2) or (3), a problem is caused if the semiconductor wafer is curved or warped. For instance, even in the case of selecting and using semiconductor wafers in which the degree of curve or warp is below 2 .mu.m at the time when the monocrystalline silicon region isolated from the semiconductor substrate by an insulation layer is formed, a warp of at least 10 .mu.m or more is caused in many of those semiconductor wafers when integrated circuit elements are formed on those wafers. This is a serious obstacle to the formation of fine patterns.
The warp is caused when the integrated circuit elements are manufactured by a heat treatment performed at 900 to 1,000.degree. C. As the coefficients of the thermal expansion of the monocrystalline silicon layer and the insulation layer differ from each other, the monocrystalline silicon layer and insulation layer expand at different rates during the thermal treatment process. It is understood that the greater the inequality of temperature distribution in the wafer, the greater the degree of the warp. Repeated execution of this thermal treatment process increases the degree of warp in the wafer and lowers the yield.
Examples of the warp caused in the isolation method (2) are introduced in "Microstructural Defects in Laser Recrystallized, Graphite Strip Heater Recrystallized and Buried Oxide Silicon-on-Insulator Systems: A Status Report" (by R. F. Pinizzato in the Journal of Crystal Growth, Vol. 63, No. 3 (1983), page 571, and examples of the warp caused in the isolation method (3) are introduced in "FIPOS Technology and its Application for LSI" (by K. Imai et. al. in IEEE TRANSACTIONS ON ELECTRON DEVICES ED-31, No. 3 (1984), page 300.
Apart from these isolation methods, tests have been made in which one of p- and n-channel transistors of CMOS device is formed on a field oxidation layer in order to prevent latch-up in the CMOS device. FIG. 1 shows an example of such a semiconductor device. This semiconductor device comprises an n-channel MOS transistor TR1 formed in the surface area of a p-type substrate 1 and a p-channel MOS transistor TR2 formed on an insulation layer 2 formed on the semiconductor substrate 1. The MOS transistor TR2 is formed by, for example, forming an n-type recrystallized polysilicon layer in the dented portion of the insulation layer 2 and doping p-type impurities in this recrystallized polysilicon layer to form p.sup.+ -type source and drain, and then forming a gate insulation film and a gate electrode on and over the recrystallized polysilicon layer.
Since a field oxide film is used as the insulation layer 2 on which the MOS transistor TR2 is formed, a thickness of the field oxide film ordinarily becomes a value over 0.5 .mu.m, for instance, about 1.0 .mu.m. Therefore, a large difference is caused between the level of the upper surface of the semiconductor substrate 1 on which the MOS transistor TR1 is formed and the level of the upper surface of the insulation layer 2 on which the MOS transistor TR2 is formed. Consequently, in the case of forming the MOS transistors TR1 and TR2 by the same manufacturing process, it is impossible to form the patterns of both MOS transistors TR1 and TR2 accurately. For instance, in order to form a contact hole pattern having a width of 1.0 to 1.5 .mu.m by applying the light of a wavelength of 500 nm onto the semiconductor structure by the use of an exposing apparatus having an ideal optical system, the maximum deviation of the level of the surface of the wafer of a single chip with respect to the focal plane has to be below a range of 0.7 to 1.4 .mu.m. Therefore, in the case of using an ordinary exposing apparatus, since the manufacturing margin or permissible deviation in surface level is small, it is difficult to form the MOS transistors TR1 and TR2 on the semiconductor substrate 1 and insulation layer 2, respectively, so they have a level difference of, e.g., 1.0 .mu.m, by the same manufacturing process.
It is also difficult to set the optimum conditions for the etching process to form contact holes for each of the MOS transistors TR1 and TR2 by the same process. Further, in the case where a polycrystalline silicon layer is formed on the field oxide film by a sputtering method and this polycrystalline silicon layer is recrystallized by applying a laser beam, it is generally understood that it is difficult to obtain island monocrystalline silicon layers from this polycrystalline silicon layer.